1. Field of the Invention
The present invention relates generally to the field of Field Programmable Gate Arrays and more specifically to an increase in the efficiency of signal line usage in an FPGA by employing RAM control lines as routing or logic resources after these lines are used to program control memory.
2. Prior Art
In a SRAM-programmed Field Programmable Gate Array (FPGA) a large proportion of the available metal planes are used by bit line and word line signals required for programming the control memory. In one commercial device approximately one-half of the total available routing resources on the second metal layer are used by RAM bit lines and of the remaining area a proportion is required by power and ground distribution. Numerically, there are 10 user signals routed from east to west on second metal in a unit tile and 16 RAM bit lines. The situation in the north/south direction is less serious with 12 user signals and 3 RAM word lines, but RAM signals still use a significant proportion of the available resources. After configuration of the device, the state of the RAM control memory is often not changed and these control signals are normally unused. A technique which could make use of these expensive resources for routing or logic within user designs would have considerable benefits. The techniques described here are most applicable to an FPGA where the control memory is partitioned into many smaller memories and the device can tolerate random values in its control memory without causing contention on tri-state routing resources. Such an FPGA is disclosed in British Pat. Application No. 9604496.1 filed on Mar. 1, 1996 and entitled "EMBEDDED MEMORY FOR FIELD PROGRAMMABLE GATE ARRAY". These techniques are also applicable to blocks of embedded RAM within a more conventional FPGA. The Programmable Logic Data Book published in 1996 by Xilinx, Inc., contains relevant information and is incorporated herein by reference. Other relevant information may be obtained from the following:
1) "Semiconductor Memories", Betty Prince, Wiley 1991. PA1 2) "The Design of a New FPGA Architecture", Anthony Stansfield and Jan Page in Lecture Notes in Computer Science 975, Springer Verlog 1995; PA1 3) U.S. patent application Ser. No. 08/460,314 filed on Jun. 2, 1995 by inventor Steven Churcher and entitled "Sense Amplifier For Reading Logic Devices".
The latter reference discloses a preferred sense amplifier for use in the present invention and is therefore incorporated herein by reference.